1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and in particular, to a power control circuit that improves power efficiency, a method of controlling a power control circuit and a DLL circuit including power a control circuit.
2. Related Art
In general, a DLL circuit generates an internal clock that has a more advanced phase than a reference clock (obtained by converting an external clock). The internal clock that is used in a semiconductor integrated circuit is delayed by a clock buffer and a transmission line to generate a phase difference between the internal clock and the external clock. Due to the phase difference, the output data access time is made longer. The DLL circuit is used to prevent the output data access time from being extended. As such, the DLL circuit controls the internal clock to have a more advanced phase than the external clock for a predetermined time, to thereby increase an effective data output period.
The DLL circuit includes a feedback loop that compares a feedback clock (generated by modeling the delay amount of the internal clock until it is transmitted to the data output buffer) with the reference clock. A delay block that delays the reference clock to generate the internal clock is configured to perform a coarse delay operation or a fine delay operation according to the phase difference between the feedback clock and the reference clock. The delay block selects one of the coarse delay mode and the fine delay mode depending on whether or not a locking completion signal transmitted from an operation mode setting apparatus is enabled. With this operation, the DLL circuit gives a fixed coarse delay time to the reference clock when the locking completion signal is enabled, and performs an operation to change the fine delay time, to thereby change the delay value that is given to the reference clock.
The operation cycle of the DLL circuit is determined by a toggle timing of one of a plurality of pulse signals, which are generated by a clock generating block. One of the plurality of pulse signals has a cycle larger than the reference clock (for example, two times), and is enabled at every predetermined number of cycles of the reference clock (for example, 20 cycles). The phase comparing block and the operation mode setting block of the DLL circuit operate in response to the one pulse signal. Therefore, the enable cycle of the pulse signal becomes the operation cycle of the DLL circuit.
As such, the DLL circuit detects the phase difference between the reference clock and the feedback clock at every operation cycle to determine whether or not locking is completed. Then, if it is determined that locking is completed, the DLL circuit does not significantly change the delay amount, which is applied to the reference clock. Therefore, the feedback loop that constitutes the DLL circuit is not necessarily activated after locking is completed.
However, the feedback loop of the DLL circuit is activated after locking is completed, and then power is continuously consumed. As semiconductor integrated circuits with low power consumption profiles may be advantageous for certain applications, it is desirable to improve the power efficiency of integrated circuits by eliminating power consumption factors.